The present disclosure relates to the field of semiconductor structures, and particularly to metal-contamination-free through-substrate via structures and methods of manufacturing the same.
In recent years, “three dimensional silicon” (3DSi) structures have been proposed to enable joining of multiple silicon chips and/or wafers that are mounted on a package or a system board. The 3DSi structures employ conductive via structures, which are referred to as “through-substrate via” structures or “TSV” structures, which provide electrical connection through the substrate of a semiconductor chip. The TSV structures increase the density of active circuits that are integrated in a given space. Such 3DSi structures employ through-substrate vias (TSVs) to provide electrical connection among the multiple silicon chips and/or wafers.
A conventional TSV structure typically employs a copper via structure that extends through the substrate of a semiconductor chip. The copper via structure is laterally electrically isolated from the substrate by a silicon oxide dielectric liner. The silicon oxide dielectric liner does not prevent metallic materials from diffusing through. Thus, residual copper material generated during the chemical mechanical polishing of an embedded end of a copper via structure can be smeared onto an end surface of the silicon oxide dielectric liner, and subsequently diffuse through the silicon oxide dielectric liner and into a semiconductor material within the substrate. Diffusion of such residual copper material into the semiconductor material can create detrimental effects such as electrical shorts within semiconductor devices in the substrate.